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HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 1 - 2003 hynix semiconductor inc. cmos image sensor with image signal processing HV7151SP hynix semiconductor inc. preliminary release version 0. 7
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 2 - 2003 hynix semiconductor inc. revision history revision script date comments 0.0 2003 - june HV7151SP preliminary is released 0.1 2003 - june HV7151SP version 0. 1 is released 0.2 2003 - july HV7151SP version 0.2 is released 0.5 2003 - august HV7151SP version 0.5 is released 0.6 2003 - november frame rate calculation is added 0.7 2004 - january enb setting guide information and recommend circuit information is added copyright by hynix semiconductor inc., all right reserved 2003
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 3 - 2003 hynix semiconductor inc. contents general description ................................ ................................ ................................ .................... 5 features ................................ ................................ ................................ ................................ .... 5 block diagram ................................ ................................ ................................ ........................... 6 pixel structure ................................ ................................ ................................ ........................... 7 pin diagram ................................ ................................ ................................ ............................... 8 pin diagram ................................ ................................ ................................ ............................... 9 functional description ................................ ................................ ................................ .............. 10 pixel architecture ................................ ................................ ................................ .............. 10 sensor imaging operation ................................ ................................ ................................ .. 10 on - chip frequency synthesizer ................................ ................................ .......................... 11 11bit on - chip adc ................................ ................................ ................................ .............. 11 gamma correction ................................ ................................ ................................ ............. 11 color interpolation ................................ ................................ ................................ .............. 12 sub - sampling mode ................................ ................................ ................................ ........... 12 scaling mode ................................ ................................ ................................ .................... 12 color correction ................................ ................................ ................................ ................. 12 color space conversion & reverse color space conversion ................................ .................. 13 luminance processing ? contrast, brightness adjustment ................................ .................... 14 chrominance processing ? saturation adjustment ................................ ................................ 14 edge enhancement ................................ ................................ ................................ ........... 14 chroma suppression ................................ ................................ ................................ .......... 14 automatic flicker cancellation ................................ ................................ ............................ 14 output formatting ................................ ................................ ................................ .............. 15 auto exposure control ................................ ................................ ................................ ....... 15 auto white balance ................................ ................................ ................................ ........... 15 register description ................................ ................................ ................................ ................. 16 anti - banding configuration ................................ ................................ ................................ ........ 60 frame timing ................................ ................................ ................................ ........................... 60 output data according to video mode ................................ ................................ ........................ 66 bayer data format ................................ ................................ ................................ ................... 79 i2c chip interface ................................ ................................ ................................ ..................... 80 ac/dc characteristics ................................ ................................ ................................ .............. 82 electro - optical characteristics ................................ ................................ ................................ .. 85
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 4 - 2003 hynix semiconductor inc. package information ................................ ................................ ................................ ................. 86 reference circuit information ................................ ................................ ................................ ..... 88 memo ................................ ................................ ................................ ................................ .... 89
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 5 - 2003 hynix semiconductor inc. general description HV7151SP is a highly integrated single chip cmos color image sensor implemented by proprietary hynix 0. 18 um cmos sensor process realizing high sensitivity and wide dynamic range. a ctive pixel array is 11 64 x886 . each active pixel composed of 4 transistors , it has a micro - lens to enhance sensitivity, and c onverts photon energy to analog pixel voltage. on - chip 11 bit analog to digital converter ( ad c) digitize s analog pixel voltage, and on - chip correlated double sampling (cds) scheme reduces fixed pattern noise (fpn) dramatically. general image processing func tions are implemented to diversify its applications, and various output formats are supported for the sensor to easily interface with different video codec chips. the integration of sensor function and image processing functions make HV7151SP especially ve ry suitable for mobile imaging systems such as digital still camera, pc input camera and imt - 2000 phone?s video part that requires very low power and system compactness. features n o ptical f ormat : 1/4 inch / pixel size : 3.2 m m x 3.2 m m n active pixel arra y : 11 70 x 886 n multiple video modes : 1152x864(mega), 640x480(vga), 576x432(1/4 mega), 352x288(cif), 320x240(qvga), 288x216(1/16 mega), 176x144(qcif) n bayer rgb c olor filter array / micro - lens for high sensitivity n on - chip frequency synthesizer n on - chip 11 bit analog to digital converter n correlated d ouble s ampling (cds) for reduction of fixed pattern noise (fpn) n automatic flicker cancellation (afc) n automatic black level calibration (ablc) n gamma c orrection by programmable piecewise linear approximation n 5x5 color interpolation n color c orrection by programmable 3x3 matrix operation n color s pace c onversion from rgb to y c bcr and reverse conversion from ycbcr to rgb n image adjustment :contrast, brightness, saturation, edge enhancement, chroma suppression n various o u tput f ormats: ccir - 601, ccir - 656 compatible ycbcr 4:2:2, ycbcr 4:4:4, rgb 4:4:4, rgb 565, bayer n 8bit/16bit data bus mode n auto matic exposure control and auto matic white balance control n power s a ve m ode
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 6 - 2003 hynix semiconductor inc. n typical supply voltage : internal 1.8v and i/o 2.5 v n operation temperature : - 1 0 ~ +5 0 degree s c elsius n package type s : clcc 40 pin , cob(chip - on - board), cof(chip - on - flex) block diagram analog signal processing digital signal processing pixel array 1170x886 timing control config registers i2c slave 11 bit adc resetb mclk enb sck sda vclk vsync hsync y[7:0] c[7:0]
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 7 - 2003 hynix semiconductor inc. pixel structure
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 8 - 2003 hynix semiconductor inc. pin diagram 16 17 18 19 20 21 22 23 24 25 5 4 3 2 1 35 34 33 32 31 30 29 28 27 26 6 7 8 9 10 11 12 13 14 15 HV7151SP clcc 40 pin top view dvddc dgndc c[7] c[6] c[5] c[4] c[3] c[2] c[1] c[0] y[7] y[6] y[5] y[4] y[3] y[2] y[1] y[0] dgndi dvddi dgndi dvddih mclk vclk hsync vsync ainp ainn avdd agnd avddh dvddi dgndi enb resetb strobe sck sda dgndih dvddih 40 39 38 37 36
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 9 - 2003 hynix semiconductor inc. pin diagram c[7:0] sho uld be set up as pull - up or pull - down when 8bit output mode is used. pin type symbol description 36 - 40, 1 - 3 b y[7:0] video luminance data[7:0] 4 g dgndi digital ground for i/o driver 5 p dvddi 1.8v digital power for i/o driver 6 p dvddc 1.8v power for internal digital block 7 g dgndc ground for internal digital block 8 - 15 b c[7:0] video chrominance data[7:0] 16 ph dvddih 2.5v digital power for i/o driver 17 g dgndih digital ground for i/o driver 18 b sda i2c standard data i/o port 19 i sck i2c clo ck input 20 o strobe strobe signal output 21 i resetb sensor reset, low active 22 i enb sensor sleep mode is controlled externally by this pin when sleep mode register bit is low. enb low : sleep mode, enb high : normal mode 23 g dgndi digital ground f or i/o driver 24 p dvddi 1.8v digital power for i/o driver 25 ph avddph 2.5v analog power for pixel block 26 g agnd analog ground for analog block 27 p avdd 1.8v power for internal analog block 28 ai ainn analog input minus for test adc 29 ai ainp an alog input plus for test adc 30 b vsync video frame synchronization signal. vsync is active at start of image data frame. 31 b hsync video horizontal line synchronization signal. image data is valid, when hsync is high. 32 b vclk video output clock 33 i mclk master input clock 34 ph dvddih 2.5v digital power for i/o driver 35 g dgndi digital ground for i/o driver
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 10 - 2003 hynix semiconductor inc. functional description pixel architecture pixel architecture is a 4 transistor nmos pixel design. the additional use of a dedicated transf er transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible. furthermore, micro - lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved . enb setting guid e infor mation for normal stand - by mode it is necessary that this kind of initialization sequence for the normal stand - by mode of hv71 51s p after system power on ex) if mclk = 19.2 [mhz] and pll 2x, => 2 .68 [mcycle] / 38.4 [mhz] = 69.79 ms the time period of enb high value have to keep for 69.79 [ms] or more sensor imaging operation imaging operation is implemented by the offset mechanism of integration domain and scan domain(rolling shutter scheme). first integration plane is initi ated, and after the programmed integration time is elapsed, scan plane is initiated, then image data start being produced. dvdd/avdd resetb mclk vsync i2c enb don ? t care low low low low system power on initializat ion sequence 2. 68 [ mcycle ] for logic stable time 2. 56 [ mcycle ] for 1'st vsync out more than 4cycle don ? t care 1ms sensor operation sequence sensor power down sequence camera mode video stream 1 ? st vsync out dvdd/avdd resetb mclk vsync i2c enb don ? t care low low low low system power on initialization sequence more than 4cycle don ? t care 1ms sensor operation sequence sensor power down sequence camera mode video stream 1 ? st vsync out
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 11 - 2003 hynix semiconductor inc. integration time frame 0 time time integration plane frame 0 integration plane frame 1 scan plane frame 0 scan plane frame 1 frame 1 time on - chip frequency synthesizer on - chip frequency synthesizer generates variable frequency according to the proportion of reference(prefdiv) to feedback(pfddiv) divisor. operating frequency is fully programmable and output range is 5mhz to 100mhz. 11bit on - chip adc on - chip adc converts analog pixel voltage to 11bit digital data. gamma correction piecewise linear approximation method is implemented. ten piece linear segments are supported and user - programmable.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 12 - 2003 hynix semiconductor inc. gamma transfer function in out start 0 start 1 0 128 256 384 512 1024 1536 32 64 start 2 2047 start 9 : : 8 color interpolation 5x5 linear color interpolation is used to interpolate missing r, g, or b for mosaic image data fro m pixel array . interpolation is done by moving 5x5 interpolation window by one pixel horizontally and vertically. sub - sampling mode the sub - sampling modes such as 1/4 sub - sampling and 1/16 sub - sampling are supported. the sub - sampling sequence is as below. for example 1/4 sub - sampling, row data are picked out from r,g,b bayer raw data by the rate of four to two. and after 5x5 linear color interpolation, column data also are picked out the rate of two to one. 1/16 sub - sampling is similar to 1/4 sub - sampling. scaling mode in addition to the sub - sampling mode, HV7151SP supports the scaling modes, such as 5/9 scaling vga, 5/18 scaling qvga, 1/3 scaling cif and 1/6 qcif. because HV7151SP normal image size(1152x864) is not a multiple proportion of vga/qvga or cif /qcif image size, output data and output clock of scaling mode are asymmetry. color correction generally, the color spread effect is mainly caused by color filter characteristics. the effect is compensated by 3x3 color correction operation. color correct ion matrix may be resolved by measuring sensor ? s color spread characteristics for primary color source and calculating the inverse
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 13 - 2003 hynix semiconductor inc. matrix of color spread matrix. nine registers for matrix coefficients are used in color correction operation to get the optim al pure color. the relationship between input color and color - corrected color is defined as below formula. ? ? ? ? = ? ? b g r crcm crcm crcm crcm crcm crcm crcm crcm crcm b g r 33 32 31 23 22 21 13 12 11 where r,g,b = sensor color output r ? ,g ? ,b ? = color - corrected output coefficients crcmxx are programmable from ? 127/64 ~ 1 27/64. programming register value for intended color correction matrix coefficients should be resolved by the following equations. for positive values, c rcm xx = integer(real coefficient value x 64); for negative values, c rcm xx = two? s complement(integer(re al coefficient value x 64)); real coefficien t value values from ? 127/64 ~ 127/64 can be programmed. color space conversion & reverse color space conversion both of color space conversion and reverse color space conversion are implemented by 3x3 matrix ope ration. output ranges of color space conversion and reverse conversion are existed two modes. one is 16 y 235, 16 cb,cr 240 & 16 reverse - r,g,b 235 and another is 0 y,cb,cr 255 & 0 reverse - r,g,b 255. these different modes are selected by control r egister. for color space conversion and reverse conversion matrix, the equation from ccir - 601 standard is normally used. < conversion equation > mode 1 : 255 ~ 0 : 255 ~ 0 : 255 ~ 0 : 128 128 0 081 . 0 419 . 0 500 . 0 500 . 0 331 . 0 169 . 0 114 . 0 587 . 0 299 . 0 range range range b g r cr cb y ? ? + ? ? ? ? - - - - = ? ? mode 2 : 240 ~ 16 : 240 ~ 16 : 235 ~ 16 : 128 128 16 071 . 0 368 . 0 439 . 0 439 . 0 291 . 0 148 . 0 098 . 0 504 . 0 257 . 0 range range range b g r cr cb y ? ? + ? ? ? ? - - - - = ? ?
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 14 - 2003 hynix semiconductor inc. in the above equations, r, g, and b are gamma - corrected values. < reverse conversion equation > 235 ~ 16 255 ~ 0 : 235 ~ 16 255 ~ 0 : 235 ~ 16 255 ~ 0 : 128 128 772 . 1 1 0 344 . 0 1 714 . 0 0 1 402 . 1 or range or range or range cb y cr b g r ? ? - - ? ? - - = ? ? same matrix equations are applied to mode1 and mode2 in the reverse color space conversion. and previously, output ranges 0 ~ 255 or 16 ~ 235 are decided by input ranges of y, cb,cr. luminance processing ? contrast, brightness adjustment for contrast adjustment, y digital channels are scaled by the contrast factor. contrast factor resolution is 1/128 and its range is 0 ~ 255/128. for brightness adjustment, there is added a brig htness factor to y digital channels. brightness factor range is ? 128 ~ 127 and register value for brightness adjustment is following below. for positive values, brightness factor = integer ; for negative values, brightness factor = two? s complement (integer) ; for example, if brightness factor is 3, register value is 8 ? h03 and if brightness factor is - 3, register value is 8 ? hfd. chrominance processing ? saturation adjustment for saturation adjustment , cb,cr digital channels are scaled by the saturation factor . saturation factor resolution is 1/128 and its range is 0 ~ 255/128. edge enhancement edge enhancement is performed for increasing sharpness of image. edge weight factor is user - programmable and its range is 0.3 ~ 1.0. chroma suppression chroma suppr ession is performed in the dark environment for suppressing the color and decreasing dark bad pixel effect. suppression level is varied in accordance with amplifier gain and saturation level is user - programmable. automatic flicker cancellation banding nois e, caused by difference between frequency of light sources and frequency of integration time of pixel, is always generated in cmos image sensor. for automatic flicker cancellation, integration time is adjusted automatically in accordance with frequency of light sources.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 15 - 2003 hynix semiconductor inc. output formatting the output formats such as ycbcr 4:2:2 , ycbcr 4:4:4, rgb 4:4:4, rgb 5:6:5 and bayer raw data are supported. possible output bus widths are 8 bits and 16bits, and the sequence of cb and cr or r and b are programmable. the o utput formats are compatible with recommendation ccir - 601, ccir - 656. auto exposure control y mean value is continuously calculated every frame, and the integration time or amp gain value are increased or decreased according to difference between target y mean value and current frame y mean value. auto white balance cb/cr frame mean value is calculated every frame and according to cb/cr frame mean values ? displacement from cb/cr white target point, r/b scaling values for r/b data are resolved.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 16 - 2003 hynix semiconductor inc. register d escription addres s default symbol (hex) (hex) description devid 00 5 0 device id sctra 01 13 sensor control a sctrb 02 00 sensor control b sctrc 03 01 sensor control c rsau 08 00 row start address upper rsal 09 02 row start address lower csau 0a 00 column start address upper csal 0b 02 column start address lower wihu 0c 03 window height upper wihl 0d 60 window height lower wiwu 0e 04 window width upper wiwl 0f 80 window width lower hblu 10 00 horizontal blank time upper hbll 11 d0 horizont al blank time lower vblu 12 00 vertical blank time upper vbll 13 08 vertical blank time lower rgain 14 08 red color gain ggain 15 08 green color gain bgain 16 08 blue color gain ampgain 17 08 amp gain for pixel output ampmin 18 10 amp gain minim um value ampmax 19 28 amp gain maximum value ampnom 1a 18 amp gain normal value ampbias 1b 13 cds bias , amplifier bias rstclmp 1c 07 reset level clamp enable, reset value
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 17 - 2003 hynix semiconductor inc. adcbias 20 2 adc bias control oredi 21 7f adc initial offset value for op tical black red ogrni 22 7f adc initial offset value for optical black green oblui 23 7f adc initial offset value for optical black blue blkth 27 ff black level threshold value ispfun 30 ff image signal p rocessing f unctions enable outfmt 31 31 image d ata o utput f ormat outinv 32 00 output s ignal inversion edgewt 33 02 edge enhancement weight crcm11 34 4c color correction matrix coefficient 11 crcm12 35 ec color correction matrix coefficient 12 crcm13 36 08 color correction matrix coefficient 13 c rcm21 37 f0 color correction matrix coefficient 21 crcm22 38 76 color correction matrix coefficient 22 crcm23 39 db color correction matrix coefficient 23 crcm31 3a fe color correction matrix coefficient 31 crcm32 3b e8 color correction matrix coeffici ent 32 crcm33 3c 5a color correction matrix coefficient 33 gmap0 40 00 start point for gamma line segment 0 gmap1 41 04 start point for gamma line segment 1 gmap2 42 1c start point for gamma line segment 2 gmap3 43 34 start point for gamma line segmen t 3 gmap4 44 54 start point for gamma line segment 4 gmap5 45 78 start point for gamma line segment 5 gmap6 46 90 start point for gamma line segment 6 gmap7 47 a4 start point for gamma line segment 7 gmap8 48 e0 start point for gamma line segment 8 g map9 49 f4 start point for gamma line segment 9 g ma s0 50 40 slope value for gamma line segment 0 g ma s1 51 80 slope value for gamma line segment 1
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 18 - 2003 hynix semiconductor inc. g ma s2 52 60 slope value for gamma line segment 2 g ma s3 53 40 slope value for gamma line segment 3 g ma s4 5 4 24 slope value for gamma line segment 4 g ma s5 55 18 slope value for gamma line segment 5 g ma s6 56 14 slope value for gamma line segment 6 g ma s7 57 0f slope value for gamma line segment 7 g ma s8 58 05 slope value for gamma line segment 8 g ma s9 59 02 s lope value for gamma line segment 9 brighty 5a 00 brightness factor for brightness adjustment satcr 5b 80 saturation factor for saturation adjustment satcb 5c 80 saturation factor for saturation adjustment e dthlo 5d 05 edge enhancement vth low edthhi 5e 80 edge enhancement vth high chsupfnc 5f 64 chroma suppression function aemode1 60 bd auto e xposure control mode 1 aemode2 61 5d auto e xposure control mode 2 cscmode 62 00 color space conversion mode select inth 63 13 integration time high int m 64 88 integration time middle intl 65 00 integration time low aetrgt 66 70 luminance target value aelfbnd 67 a2 y frame mean value displacement boundary aeulbnd 68 2a y frame mean value displacement from ae target where ae update speed transits f rom 2x integration unit speed to 1x integration unit speed asfcon 69 00 ae speed and frame control aesteph 6a 02 ae anti - banding step high aestepm 6b ee ae anti - banding step middle aestepl 6c 00 ae anti - banding step low aeinth 6d 3a ae integration tim e limit high aeintm 6e 98 ae integration time limit middle
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 19 - 2003 hynix semiconductor inc. aeintl 6f 00 ae integration time limit low awbmode1 70 41 auto white balance control m ode 1 awbmode2 71 02 auto white balance control m ode 2 cbtrgt 73 80 cb frame mean value for awb. crtrg t 74 80 cr frame mean value for awb. awblbnd 75 02 cb, cr frame mean displacement from cb target and cr target where awb goes into lock state awbulbnd 76 06 displacement from ideal white pixel where awb release from lock state awbwbnd 77 30 displacemen t from ideal white pixel where awb recognizes a pixel as a white pixel affected by light source aestat 7b ro current ae operation status awbstat 7c ro current awb operation status lumean 7d ro active y frame mean value cbmean 7e ro active cb frame mean value crmean 7f ro active cr frame mean value bndgmin 80 08 minimum gain value with anti - banding enabled bndgmax 81 18 maximum gain value with anti - banding enabled awbwht 8a c8 during cb, cr frame mean value calculation, awb discards pixel of which lu minance is larger than this register value. awbblk 8b 0a during cb, cr frame mean value calculation, awb discards pixel of which luminance is smaller than this register value. awbvalid 8c 02 awb update when the number of valid color pixel is larger than (this minimum value x 64) dpcmode 90 01 dark bad pixel concealment mode selection dpcintvalh 91 29 integration time value high byte where filtering operation gets active when dark bad pixel concealment mode is enabled. dpcintvalm 92 da integration time value middle byte where filtering operation gets active when dark bad pixel concealment mode is enabled. dpcintvall 93 49 integration time value lower byte where filtering operation gets active when dark bad pixel concealment mode is enabled. dpcgth 94 2 0 neighbor - differential threshold value that specify g dark bad pixel dpccth 95 20 neighbor - differential threshold value that specify r/b dark bad pixel dpcgainval 96 38 reference of amp gain which dark bad pixel concealment mode is enabled or disabled conty 97 80 contrast factor for contrast adjustment pctra a0 01 pll control mode a pctrb a1 1d pll control mode b pfddivh a4 00 pll feedback divisor high
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 20 - 2003 hynix semiconductor inc. pfddivl a5 02 pll feedback di visor low pxnumh b9 04 pi xel number high pxnuml ba 00 pi xel number low stthval bb 30 stable range variation chthval bc 20 frequency change variation afcmode bd 00 afc mode control i nteg t50h c0 02 50hz integration time high i nteg t50m c1 ee 50hz integ ration time middle i nteg t50l c2 00 50hz integration time low i nteg t60h c3 02 60hz integration time high i nteg t60m c4 71 60hz integration time middle i nteg t60l c5 00 60hz integration time low
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 21 - 2003 hynix semiconductor inc. device id [devid : 00h : 50h] 7 6 5 4 3 2 1 0 product id revision number 0 1 0 1 0 0 0 0 high nibble represents sensor resolution, low nibble represents revision number. sensor control a [sctra : 01h : 13h] 7 6 5 4 3 2 1 0 reserved x - flip y - flip video mode 0 0 0 1 0 0 1 1 x - flip image is horizontally fl ipped y - flip image is vertically flipped 111 1/6 scaling qcif mode 110 1/3 scaling cif mode 101 5/18 scaling qvga mode 100 5/9 scaling vga mode 011 5x5 linear color interpolation mode 010 1/4 sub - sampling mode 001 1/16 sub - samplin g mode video mode 000 bayer output mode sensor control b [sctrb : 02h : 00h] 7 6 5 4 3 2 1 0 ae/awb block sleep datapath block sleep analog block sleep sleep mode strobe enable clock division 0 0 0 0 0 0 0 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 22 - 2003 hynix semiconductor inc. ae/awb block sleep ae/awb block goes into sleep m ode with this bit set to high. datapath block sleep image processing datapath block goes into sleep mode with this bit set to high. analog block sleep all internal analog block goes into sleep mode with this bit set to high. with all digital block sleep active, sensor goes into power down mode. sleep mode all internal digital and analog block goes into sleep with this bit set to high. strobe enable when strobe signal is enabled by this bit, strobe pin will indicates when strobe light should be splashed in the dark environment to get adequate lighted image. clock division divide s input master clock (imc) for internal use. internal divided clock frequency(dcf) is defined as master clock frequency(mcf) divided by specified clock divisor . internal divided cl ock frequency(dcf) is as follows. 0 00 : mcf, 0 01 : mcf/2, 0 10 : mcf/4, 0 11 : mcf/8 100 : mcf/16, 101 : mcf/32, 110 : mcf/64, 111 : mcf/128 sensor control c [sctrc : 03h : 01h] 7 6 5 4 3 2 1 0 reserved hsync in vblank vblank unit unified gai n black level data enable black level compens - ation 0 0 0 0 0 0 0 1 hsync in vblank 0 : there are no valid hsync during valid vblank. 1 : there are valid hsync during valid vblank. at time, vblank unit must be line unit. vblank hsync vblank unit 0 : line unit. vblank unit is based on multiple line period time of sensor.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 23 - 2003 hynix semiconductor inc. 1 : pixel unit. vblank unit is based on multiple pixel clock period time of sensor. unified gain 1 : g analog gain is used for r,g and b analog gain. 0 : r,g and b an alog gain is used individually . black level data enable hsync is generated for light - shielded pixels in 4 lines. black level compensation black level average values of light - shielded pixels are compensated when active image data is produced. row start address upper [rsau : 08h : 00h] 7 6 5 4 3 2 1 0 reserved row start address upper 0 0 0 0 0 0 0 0 row start address lower [rsal : 09h : 02h] 7 6 5 4 3 2 1 0 row start address lower 0 0 0 0 0 0 1 0 row start address register defines the row start ad dress of image read out operation. column start address upper [csau : 0ah : 00h] 7 6 5 4 3 2 1 0 reserved column start address upper 0 0 0 0 0 0 0 0 column start address lower [csal : 0bh : 02h] 7 6 5 4 3 2 1 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 24 - 2003 hynix semiconductor inc. column start address lower 0 0 0 0 0 0 1 0 column start address register defines the column start address of image read out operation. window height upper [wihu : 0ch : 03h] 7 6 5 4 3 2 1 0 reserved window height upper 0 0 0 0 0 0 1 1 window height lower [wihl : 0dh : 60h] 7 6 5 4 3 2 1 0 window height lower 0 1 1 0 0 0 0 0 window height register defines the height of image to be read out. window width upper [wiwu : 0eh : 04h] 7 6 5 4 3 2 1 0 reserved window width upper 0 0 0 0 0 1 0 0 window width lower [wiwl : 0fh : 80h] 7 6 5 4 3 2 1 0 window width lower 1 0 0 0 0 0 0 0 window width address register defines the width of image to be read out.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 25 - 2003 hynix semiconductor inc. horizontal blank time upper [hblu : 10h : 00h] 7 6 5 4 3 2 1 0 horizontal blank time upper 0 0 0 0 0 0 0 0 horizontal blank time lower [hbll : 11h : d0h] 7 6 5 4 3 2 1 0 horizontal blank time lower 1 1 0 1 0 0 0 0 hblank time register defines data blank time between current line and next line by using sensor clock period unit , and should be larger than 208 ( d0 h). vertical blank time upper [vblu : 12h : 00h] 7 6 5 4 3 2 1 0 vertical blank time upper 0 0 0 0 0 0 0 0 vertical blank time lower [vbll : 13h : 08h] 7 6 5 4 3 2 1 0 vertical blank time lower 0 0 0 0 1 0 0 0 vblank time register defines active high duration o f vsync output. active high vsync indicates frame boundary between continuous frames. each sensor has a little different photo - diode characteristics so that the sensor provides internal adjustment registers that calibrate s internal sensing circuit in ord er to get optimal performance. sensor characteristics adjustment register s are as below. red color gain [rgain : 14h : 08h] 7 6 5 4 3 2 1 0 reserved red amplifier gain
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 26 - 2003 hynix semiconductor inc. 0 0 0 0 1 0 0 0 green color gain [ggain : 15h : 08h] 7 6 5 4 3 2 1 0 reserved green amplifier gain 0 0 0 0 1 0 0 0 blue color gain [bgain : 16h : 08h] 7 6 5 4 3 2 1 0 reserved blue amplifier gain 0 0 0 0 1 0 0 0 there are three color gain registers for r, g, b pixels, respectively . programmable range is from 0.5x ~ 2.5x. effectiv e gain = 0.5 + b<4:0>/16. these registers may be used for white balance and color effect with independent r,g,b color control . default gain is 1x. amp gain [ampgain : 17h : 08h] 7 6 5 4 3 2 1 0 reserved amp gain 0 0 0 0 1 0 0 0 amp gain is common gain for r, g, b channel and used for auto exposure control. programmable range is from 0.5x ~ 8.5x. default gain is 1x. gain = 0.5 + b<6:0>/16 amp gain minimum value [ampmin : 18h : 10h] 7 6 5 4 3 2 1 0 reserved amp gain minimum 0 0 0 1 0 0 0 0 amp gain minimum value is minimum value of amplifier gain when sensor adjusts amplifier gain for auto exposure control. programmable range is same as amp gain. recommended value is 1.5x. amp gain maximum value [ampmax : 19h : 28h] 7 6 5 4 3 2 1 0 reserved am p gain maximum
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 27 - 2003 hynix semiconductor inc. 0 0 1 0 1 0 0 0 amp gain maximum value is maximum value of amplifier gain when sensor adjusts amplifier gain for auto exposure control. programmable range is same as amp gain. recommended value is 3x. amp gain normal value [ampnom : 1 ah : 18h] 7 6 5 4 3 2 1 0 reserved amp gain normal 0 0 0 1 1 0 0 0 amp gain normal value is reference value of amp gain when sensor adjusts amp gain for auto exposure control. first, sensor controls integration time before adjusting amp gain for auto ex posure control. after integration time is changed to the minimum or maximum value, sensor adjusts amp gain from this register value. refer to figure of ae mode1 register(60h). programmable range is same as amp gain. recommended value is 2x. asp bias [ aspbias : 1bh : 13h] 7 6 5 4 3 2 1 0 reserved pixel bias amplifier bias 0 0 0 1 0 0 1 1 pixel bias controls the amount of current in internal pixel bias circuit to amplify pixel output effectively. the larger register value increases the amount of curr ent. amplifier bias controls the amount of current in internal amplifier bias circuit to amplify pixel output effectively. the larger register value increases the amount of current. reset level clamp [rstclmp : 1ch : 07h] 7 6 5 4 3 2 1 0 reserved clam p on reset level clamp 0 0 0 0 0 1 1 1 because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is captured as black image in image sensor regardless of correlated double sampling. to solve this extraordinary phe nomenon, we adopt the method to clamp reset data voltage. reset level clamp
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 28 - 2003 hynix semiconductor inc. controls the reset data voltage to prevent inversion of extremely bright image. the larger register value clamps the reset data level at highest voltage level. default value is 7 t o clamp the reset data level at appropriate voltage level. adc bias [adcbias : 20h : 02h] 7 6 5 4 3 2 1 0 reserved adc bias 0 0 0 0 0 0 1 0 adc bias controls the amount of current in adc bias circuit to operate adc effectively. adc initial offset v alue for optical black red [oredi : 21h : 7fh] 7 6 5 4 3 2 1 0 red pixel black offset 0 1 1 1 1 1 1 1 adc initial offset value for optical black green [ogrni : 22h : 7fh] 7 6 5 4 3 2 1 0 green pixel black offset 0 1 1 1 1 1 1 1 adc initial offse t value for optical black blue [oblui : 23h : 7fh] 7 6 5 4 3 2 1 0 blue pixel black offset 0 1 1 1 1 1 1 1 these registers control the offset voltage of adc that changes the black level value for light - shielded pixels, r,g,b respectively. register bit f unctions are composed as follows. pixel black offset[7] the bit specifies whether to subtract or add offset voltage in adc input for light - shielded pixels. pixel black offset[6:0] this value specifies the amount of offset voltage for light - shielded pixel s.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 29 - 2003 hynix semiconductor inc.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 30 - 2003 hynix semiconductor inc. black level threshold value [blkth : 27h : ffh] 7 6 5 4 3 2 1 0 black level threshold 1 1 1 1 1 1 1 1 the register specifies the maximum value that determines whether light - shielded pixel output is valid. when light - shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 31 - 2003 hynix semiconductor inc. isp function enable [ispfun : 30h : ffh] 7 6 5 4 3 2 1 0 reserved contrast adjustment chroma suppression edge enhancement color space conversion color correction color interpolation ga mma correction 0 1 1 1 1 1 1 1 contrast adjustment 0 : disable. 1 : enable. y output m ultiplied by contrast factor chroma suppression 0 : disable. 1 : enable. chroma suppressed cb,cr output edge enhancement 0 : disable. 1 : enable. color spac e conversion 0 : disable. r,g,b output 1 : enable. y,cb,cr output color correction 0 : disable. 1 : enable. color interpolation 0 : disable. 1 : enable. gamma correction 0 : disable. normal bayer output 1 : enable. gamma corrected bayer output
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 32 - 2003 hynix semiconductor inc. out put format [outfmt : 31h : 31h] 7 6 5 4 3 2 1 0 gamma - corrected bayer bayer 8bit output cb/b first y first ycbcr 4:4:4 / 4:2:2 rgb 4:4:4 rgb 565 8 bit output 0 0 1 1 0 0 0 1 gamma - corrected bayer gamma - corrected bayer data are output when bayer mode is set in sctra register. bayer 8bit output bayer data is output with 8bit mode, two lsb of 11 bit bayer data is stripped out. cb/b first cb (b) pixel in front of cr (r) pixel in 16bit or 8bit video data output modes . y first y pixel in front of cb and cr p ixels in 8bit video output mode . this option is meaningful only with ycbcr 4:2:2 8bit output mode. ycbcr 4:4:4 / 4:2:2 this bit is high, output format is ycbcr 4:4:4 16bit mode, otherwise output format is ycbcr 4:2:2 8bit/16bit mode. rgb 4:4:4 r,g,b 24bi t data for a pixel is produced with 16bit output mode. rgb 565 data format of rgb 565 mode is composed with {r[7:3]/g[7:5]} , {g[4:2]/b[7:3]} or {b[7:3]/g[7:5]}, {g[4:2]/r[7:3]}. outfmt[5](cb/b first) register affects above data form. 8 bit output imag e data is produced only in y[7:0]. c[7:0] should be discarded. default mode of output format is ycbcr 4:2:2 8bit mode. output signal inversion [outinv : 32h : 00h] 7 6 5 4 3 2 1 0 reserved clocked hsync vsync inversion hsync inversion vclk inversion 0 0 0 0 0 0 0 0 clocked hsync in hsync, vclk is embedded, that is, hsync is toggling at vclk rate during normal hsync time vsync inversion vsync output polarity is inverted hsync inversion hsync output polarity is inverted
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 33 - 2003 hynix semiconductor inc. vclk inversion vclk output p olarity is inverted edge enhancement weight [edgewt : 33h : 02h] 7 6 5 4 3 2 1 0 reserved edge enhancement weight 0 0 0 0 0 0 1 0 edge enhancement weight range is 0.3(3 ? h000) ~ 1(3 ? h111), and default value is 0.5(3 ? h010). as edge enhancement weight is large, the effect of edge enhancement grows stronger. color correction matrix coefficient 11 [crcm11 : 34h : 4ch] 7 6 5 4 3 2 1 0 color correction matrix coefficient 11 0 1 0 0 1 1 0 0 color correction matrix coefficient 12 [crcm 12 : 35h : ech] 7 6 5 4 3 2 1 0 color correction matrix coefficient 12 1 1 1 0 1 1 0 0 color correction matrix coefficient 13 [crcm 13 : 36h : 08h] 7 6 5 4 3 2 1 0 color correction matrix coefficient 13 0 0 0 0 1 0 0 0 color correction matrix coefficient 21 [crcm 21 : 37h : f0h] 7 6 5 4 3 2 1 0 color correction matrix coefficient 21 1 1 1 1 0 0 0 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 34 - 2003 hynix semiconductor inc. color correction matrix coefficient 22 [crcm 22 : 38h : 76h] 7 6 5 4 3 2 1 0 color correction matrix coefficient 22 0 1 1 1 0 1 1 0 color correction matrix c oefficient 23 [crcm 23 : 39h : dbh] 7 6 5 4 3 2 1 0 color correction matrix coefficient 23 1 1 0 1 1 0 1 1 color correction matrix coefficient 31 [crcm 31 : 3ah : feh] 7 6 5 4 3 2 1 0 color correction matrix coefficient 31 1 1 1 1 1 1 1 0 color c orrection matrix coefficient 32 [crcm 32 : 3bh : e8h] 7 6 5 4 3 2 1 0 color correction matrix coefficient 32 1 1 1 0 1 0 0 0 color correction matrix coefficient 33 [crcm 33 : 3ch : 5ah] 7 6 5 4 3 2 1 0 color correction matrix coefficient 33 0 1 0 1 1 0 1 0 gamma segment start points
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 35 - 2003 hynix semiconductor inc. gamma segment start points specify the start points of nine line segments for piecewise gamma approximation. current default gamma curve is very selected for optimum gray gradation. gamma point 0 [gamp0 : 40 h : 0 0h] 7 6 5 4 3 2 1 0 gamma point 0 0 0 0 0 0 0 0 0 gamma point 1 [gmap1 : 41 h : 04 h] 7 6 5 4 3 2 1 0 gamma point 1 0 0 0 0 0 1 0 0 gamma point 2 [gmap2 : 42 h : 1c h] 7 6 5 4 3 2 1 0 gamma point 2 0 0 0 1 1 1 0 0 gamma point 3 [gmap3 : 4 3 h : 34 h] 7 6 5 4 3 2 1 0 gamma point 3 0 0 1 1 0 1 0 0 gamma point 4 [gmap4 : 4 4 h : 54 h] 7 6 5 4 3 2 1 0 gamma point 4 0 1 0 1 0 1 0 0 gamma point 5 [gmap5 : 4 5 h : 78 h]
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 36 - 2003 hynix semiconductor inc. 7 6 5 4 3 2 1 0 gamma point 5 0 1 1 1 1 0 0 0 gamma point 6 [gmap6 : 4 6 h : 90 h] 7 6 5 4 3 2 1 0 gamma point 6 1 0 0 1 0 0 0 0 gamma point 7 [gmap7 : 4 7 h : a4 h] 7 6 5 4 3 2 1 0 gamma point 7 1 0 1 0 0 1 0 0 gamma point 8 [gmap8 : 4 8 h : e0 h] 7 6 5 4 3 2 1 0 gamma point 8 1 1 1 0 0 0 0 0 gamma point 9 [gmap 9 : 4 9 h : f4 h] 7 6 5 4 3 2 1 0 gamma point 9 1 1 1 1 0 1 0 0 gamma slope 0 [gmas 0 : 50 h : 40 h] 7 6 5 4 3 2 1 0 gamma slope 0 0 1 0 0 0 0 0 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 37 - 2003 hynix semiconductor inc. gamma slope 1 [gmas 1 : 51 h : 80 h] 7 6 5 4 3 2 1 0 gamma slope 1 1 0 0 0 0 0 0 0 gamma slope 2 [gmas 2 : 52 h : 60 h] 7 6 5 4 3 2 1 0 gamma slope 2 0 1 1 0 0 0 0 0 gamma slope 3 [gmas 3 : 53 h : 40 h] 7 6 5 4 3 2 1 0 gamma slope 3 0 1 0 0 0 0 0 0 gamma slope 4 [gmas 4 : 54 h : 24 h] 7 6 5 4 3 2 1 0 gamma slope 4 0 0 1 0 0 1 0 0 gamma slope 5 [gmas 5 : 55 h : 18 h] 7 6 5 4 3 2 1 0 gamma slope 5 0 0 0 1 1 0 0 0 gamma slope 6 [gmas 6 : 56 h : 14 h] 7 6 5 4 3 2 1 0 gamma slope 6 0 0 0 1 0 1 0 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 38 - 2003 hynix semiconductor inc. gamma slope 7 [gmas 7 : 57 h : 0f h] 7 6 5 4 3 2 1 0 gamma slope 7 0 0 0 0 1 1 1 1 gamma slope 8 [gmas 8 : 58 h : 05 h] 7 6 5 4 3 2 1 0 gamma slope 8 0 0 0 0 0 1 0 1 gamma slope 9 [gmas 9 : 59 h : 02 h] 7 6 5 4 3 2 1 0 gamma slope 9 0 0 0 0 0 0 1 0 brightness factor y [ brighty : 5a h : 00 h] 7 6 5 4 3 2 1 0 brightness factor y 0 0 0 0 0 0 0 0 brightness adjustment is perform ed for summ ing y data and brightness factor y. brightness factor y is two ? s complement and its range is ? 128 ~ 127. bright y = y data + brightness factor y. f or positive values , b<7:0> = integer ; f or negative values , b<7:0> = two? s complement (integer); s aturation factor cr [ satcr : 5b h : 80 h] 7 6 5 4 3 2 1 0 saturation factor cr 1 0 0 0 0 0 0 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 39 - 2003 hynix semiconductor inc. saturation factor cb [ satcb : 5c h : 80 h] 7 6 5 4 3 2 1 0 saturation factor cb 1 0 0 0 0 0 0 0 saturation adjustment is performed for multiplying cr,cb data by saturation factor cr,cb, respectively. programmable range of saturation factor cb,cr is 0 ~ 2. for instant, sat cb = cb data * b<7:0>/128. edge enhancement threshold low [ edthlo : 5d h : 05 h] 7 6 5 4 3 2 1 0 edge enhancement threshold low 0 0 0 0 0 1 0 1 edge enhancement threshold high [ edthhi : 5e h : 80 h] 7 6 5 4 3 2 1 0 edge enhancement threshold high 1 0 0 0 0 0 0 0 chroma suppression function [ chsupfnc : 5f h : 64 h] 7 6 5 4 3 2 1 0 saturation level suppression gain minimum 0 1 1 0 0 1 0 0 11 0% of difference between current cb,cr data and reference cb,cr level. so, chroma suppressed cb,cr data are equal to current cb,cr data. 10 25% of difference between current cb,cr data and reference cb,cr level. 01 50% of differ ence between current cb,cr data and reference cb,cr level. saturation level 00 75% of difference between current cb,cr data and reference cb,cr level. suppression gain minimum when amp gain is greater than suppression gain minimum, chroma suppression function is starte d.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 40 - 2003 hynix semiconductor inc.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 41 - 2003 hynix semiconductor inc. auto exposure y mean value is continuously calculated every frame, and the integration time value is increased or decreased according to the displacement between current frame y mean value and target y mean value. ae unlock boundary [68h] ae target [66h] ae lock boundary [67h] ae lock boundary [67h] ae unlock boundary [68h] 80h y frame mean ffh 0h ae mode control 1 [aem ode1 : 60h : bd h] 7 6 5 4 3 2 1 0 anti ? banding enable full window window mode ae speed ae mode 1 0 1 1 1 1 0 1
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 42 - 2003 hynix semiconductor inc. anti - banding enable when anti - banding is enabled, ae initializes integration time registers[63h - 65h] to 4 x anti - banding step value[6ah - 6ch], and integration increment/decrement amount is set to anti - banding step value in order to remove banding noise caused by intrinsic energy waveform of light sources. banding noise is inherent in cmos image sensor that adopts rolling shu tter scheme for image acquisition . in this mode, ae operates with very large unit, typically a reciprocal of (2 x power line frequency), so that minute integration time tuning is not liable. therefore, this mode is recommended for only indoor use. full w indow with this bit set to high, window mode is discarded and full image data is accounted for ae y frame mean evaluation 11 1/ 8 center weighted window mode . weighting ratio is 8:1 for inside area vs. outside area 10 1/ 8 center only window mode . 01 1/ 4 center weighted window mode . weighting ratio is 4:1 for inside area vs. outside area window mode 00 1/ 4 center only window mode . ae speed (fast)11 ? 10 ? 01 ? 00(slow) 11 gain - only control mode. only preamp gain is controlled to get optimum exposure state. 10 time - only control mode. only integration time is controlled to get optimum exposure state. 01 time - gain control mode. integration time and preamp gain are controlled to get optimum exposure state. ae mode 00 ae function is disabled ae mode control 2 [aem ode2 : 6 1 h : 5d h] 7 6 5 4 3 2 1 0 reserved gain speed integration time fine tune amp gain fine tune anti - banding minimum break ae sub - sampling mode ae analog gain control 0 1 0 1 1 1 0 1
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 43 - 2003 hynix semiconductor inc. gain speed gain update speed is specified as follows. (fast)11 ? 10 ? 01 ? 00(slow) integration time fine tune integration time fine tuning is performed when ae arrive around ae fine tune boundary to settle into ae lock state smoothly. amp gain fine tune amp gain fine tuning is performed when ae a rrive around ae fine tune boundary to settle into ae lock state smoothly. anti - banding minimum break when ae is still of out lock state despite that ae preamp analog gain update value exceeds preamp minimum gain value(18h) and integration time(63h - 65h) is reached to ae anti - banding step(6ah - 6ch), integration time(63h - 65h) is broken to less than ae anti - banding step(6ah - 6ch). ae sub - sampling mode ae statistics is executed on 1/4 of original image data to save power consumption ae analog gain control ae up dates amp gain register(17h) in order to reach optimum exposure state color space conversion mode [ csc m ode : 6 2 h : 00 h] 7 6 5 4 3 2 1 0 reserved csc mode reserved 0 0 0 1 0 0 0 0 csc mode 0 : mode 1 1 : mode 2 integration time high [int h : 6 3 h : 13 h] 7 6 5 4 3 2 1 0 integration time higher 0 0 0 1 0 0 1 1
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 44 - 2003 hynix semiconductor inc. integration time middle [intm: 6 4 h: 88 h] 7 6 5 4 3 2 1 0 integration time middle 1 0 0 0 1 0 0 0 integration time low [int l : 6 5 h: 00 h] 7 6 5 4 3 2 1 0 integration time lower 0 0 0 0 0 0 0 0 integration time value register defines the time which active pixel element evaluates photon energy that is converted to digital data output by internal adc processing. integration time is equivalent to exposure time of general camera so that inte gration time needs to be increased in dark environment and decreased according to lighting condition. maximum integration time is register maxi mum value(2 24 - 1) x sensor clock period (52ns, scf 19.2mhz) = 0.87sec. scf = sensor clock frequency luminance t arget value [aet r gt : 6 6 h : 70 h] 7 6 5 4 3 2 1 0 luminance target 0 1 1 1 0 0 0 0 this register defines the target luminance value for ae operation. ae lock & fine tune boundary [ae lfbnd : 6 7 h : a 2h] 7 6 5 4 3 2 1 0 ae fine boundary ae lock boundary 1 0 1 0 0 0 1 0 ae lock boundary specifies the displacement of y frame mean value(7dh) from ae target in which ae goes into lock state. with anti - banding is enabled, this displacement condition is discarded, and instead ae speed unlock boundary is used a s lock boundary. ae fine boundary specifies the displacement of y frame mean value(7dh) from ae target in which
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 45 - 2003 hynix semiconductor inc. ae start to tune fine integration time or amp gain in order to goes into lock state smoothly. ae unlock boundary [ae ulbnd : 6 8 h : 2a h] 7 6 5 4 3 2 1 0 ae unlock boundary 0 0 1 0 1 0 1 0 ae speed boundary 0 specifies y frame mean displacement from ae target where integration time increment/decrement speed changes from 2x (integration unit step) to 1x (integration unit step). in anti - banding mo de, this boundary is used as lock boundary for exposure control. ae speed and frame control [ asfcon : 6 9 h : 00 h] 7 6 5 4 3 2 1 0 reserved ae speed 2 y frame control cb,cr frame control 0 0 0 0 0 0 0 0 ae speed 2 (fast)11 ? 10 ? 01 ? 00(slow) 11 4 frame mean value. ( for ae ) 10 2 frame mean value. y fr ame control 01 , 00 1 frame mean value. 11 4 frame mean value. ( for awb ) 10 2 frame mean value. cb,cr frame control 01 , 00 1 frame mean value. ae speed 2 is different in use to ae speed 1. when y frame mean is out of unlock boundary, ae updates quickly amp gain register(17h) in order to reach lock boundary state. gain update speed is specified as follows. (fast)11 ? 10 ? 01 ? 00(slow) frame control register can be use 1, 2, 4 frame mean value. 4 frame mean value has a history component of previous 3 frame mean value. to use 1 frame mean value is that ae changed every frame instantly.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 46 - 2003 hynix semiconductor inc. ae anti - banding step high [ae steph : 6 a h : 02 h] 7 6 5 4 3 2 1 0 reserved integration step high er 0 0 0 0 0 0 1 0 ae anti - banding step middle [ae stepm : 6 b h : ee h] 7 6 5 4 3 2 1 0 integration step middle 1 1 1 0 1 1 1 0 ae anti - banding step low [ae step l : 6 c h : 00 h] 7 6 5 4 3 2 1 0 integration step low er 0 0 0 0 0 0 0 0 ae anti - banding step spec ifies integration time unit value that ae uses when anti - banding is enabled. anti - banding step value is resolved by the following equation. anti - banding step value = sensor operation frequency (scf) / (2x power line frequency) the default value is set with scf 19.2mhz, 50hz power line, that is, anti - banding step value = 19.2mhz / (2 x 50) = 192000d = 02ee00h ae integration time limit high [ae int h : 6 d h : 3a h] 7 6 5 4 3 2 1 0 ae integration time limit high er 0 0 1 1 1 0 1 0 ae integration time limit m iddle [ae int m : 6 e h : 98 h] 7 6 5 4 3 2 1 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 47 - 2003 hynix semiconductor inc. ae integration time limit middle 1 0 0 1 1 0 0 0 ae integration time limit low [ae int l : 6 f h : 00 h] 7 6 5 4 3 2 1 0 ae integration time limit lower 0 0 0 0 0 0 0 0 these three registers define the maximum integration time value that is allowed to sensor operation. it is desirable to set the value to multiples of ae anti - banding step to easily operate with anti - banding mode enabled. the default value is set to 1/5sec with scf set to 19.2mhz 19.2mhz / 5 = 38 40500d = 3a9800h
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 48 - 2003 hynix semiconductor inc. auto white balance cb/cr frame mean value is calculated every frame and according to cb/cr frame mean values ? displacement from cb/cr white target point, r/b scaling values for r/b data are resolved. awb unlock boundary [76h] cb/cr target [73h - 74h] awb lock boundary [75h] awvb white pixel boundary [77h] awb lock boundary [75h] awb unlock boundary [76h] awb white pixel boundary [77h] 80h cb/cr frame mean ffh 0h awb mod e control 1 [awbm ode1 : 70h : 41 h] 7 6 5 4 3 2 1 0 reserved full window reserved window mode awb speed reserved awb on 0 1 0 0 0 0 0 1 full window with this bit set to high, window mode is discarded and full image data i s accounted for ae y frame mean evaluation 1 1/ 4 center weighted window mode . weighting ratio is 4:1 for inside area vs. outside area window mode 0 1/ 4 center only window mode . awb speed (fast)11 - 10 - 01 - 00(slow) awb on auto white balance control enabled
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 49 - 2003 hynix semiconductor inc. a wb mode control 2 [aem ode2 : 71 h : 02 h] 7 6 5 4 3 2 1 0 reserved awb low speed awb sub - sampling mode awb analog gain control reserved 0 0 0 0 0 0 1 0 awb low speed with this bit set to high, analog gain speed is decreased to 1/4 of the normal speed. awb sub - sampling mode awb statistics is executed on 1/4 of original image data to save power consumption awb analog gain control awb updates r/b gain registers(14h,16h) in order to reach optimum white balance state cb frame mean value [ cbtrgt : 73 h : 80 h] 7 6 5 4 3 2 1 0 cb frame mean 1 0 0 0 0 0 0 0 this register defines cb target frame mean value for awb operation. cr frame mean value [ cr t r gt : 74 h : 80 h] 7 6 5 4 3 2 1 0 cr frame mean 1 0 0 0 0 0 0 0 this register defines cr target fra me mean value for awb operation. awb lock boundary [awblb nd : 7 5 h : 0 2h] 7 6 5 4 3 2 1 0 reserved awb lock boundary 0 0 0 0 0 0 1 0 it specifies cb/cr frame mean values ? displacement from cb/cr target (73h - 74h) value where awb
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 50 - 2003 hynix semiconductor inc. goes into lock state . a wb unlock boundary [awbu l b nd : 7 6 h : 06h] 7 6 5 4 3 2 1 0 awb unlock boundary 0 0 0 0 0 1 1 0 it specifies cb/cr frame mean value s? displacement from cb/cr target (73h - 74h) where awb is released from lock state . awb operation retains lock state unless c b/cr frame mean values ? displacement value exceeds this boundary. the value should be larger awb lock boundary . awb white pixel boundary [awbw bnd : 7 7 h : 30 h] 7 6 5 4 3 2 1 0 awb white pixel boundary 0 0 1 1 0 0 0 0 when cb/cr frame mean values ? displ acement from cb/cr target exceeds awb white pixel boundary value, awb accept frame color as it is and does not try to correct white balance deviation. current ae operation status [aest at : 7 b h : ro] 7 6 5 4 3 2 1 0 ae mode state ae lock state ro ro ro ro ro ro ro ro ae mode state this nibble represents the mode where internal y plane fsm is currently placed among time - gain control, time - only control, or gain - only control modes. ae lock state y channel fsm status, ? 0000 ? means that ae y plane is in lo ck state current a wb operation status [a wb st at : 7 c h : ro] 7 6 5 4 3 2 1 0 reserved ae/awb lock cb lock state cr lock state ro ro ro ro ro ro ro ro
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 51 - 2003 hynix semiconductor inc. ae/awb lock this single status bit indicates that ae and awb are in lock state for optimum still imag e capture. cb lock state cb channel fsm status. ? 00 ? means that awb cb plane is in lock state cr lock state cr channel fsm status. ? 00 ? means that awb cr plane is in lock state active y frame mean value [ lumean : 7 d h : ro] 7 6 5 4 3 2 1 0 y frame mea n ro ro ro ro ro ro ro ro the register reports current y plane frame mean value. active cb frame mean value [ cbmean : 7 e h : ro] 7 6 5 4 3 2 1 0 cb frame mean ro ro ro ro ro ro ro ro the register reports current cb plane frame mean value. active cr frame mean value [ crmean : 7 f h : ro] 7 6 5 4 3 2 1 0 cr frame mean ro ro ro ro ro ro ro ro the register reports current cr plane frame mean value. minimum anti - banding gain [ bndgmin : 80 h : 08h ] 7 6 5 4 3 2 1 0 minimum anti - banding gain 0 0 0 0 1 0 0 0 the register specifies the minimum limit to which ae may decrease preamp gain or y digital gain in order to get optimum exposure value while anti - banding mode is enabled and the following condition is met.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 52 - 2003 hynix semiconductor inc. ae lock boundary < (y frame mean - ae tar get) < ae unlock boundary.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 53 - 2003 hynix semiconductor inc. maximum anti - banding gain [ bndgmax : 81 h : 18h ] 7 6 5 4 3 2 1 0 maximum anti - banding gain 0 0 0 1 1 0 0 0 the register specifies the maximum limit to which ae may increase preamp gain or y digital gain in order to get optim um exposure value while anti - banding mode is enabled and the following condition is met. ae lock boundary < (ae target - y frame mean) < ae unlock boundary. awb luminance higher limit [ awbwht : 8a h : c8h ] 7 6 5 4 3 2 1 0 awb luminance higher limit 1 1 0 0 1 0 0 0 during cb/cr frame mean value calculation, awb discards pixel of which luminance value is larger than this register value. awb luminance lower limit [ awbblk : 8b h : 0ah ] 7 6 5 4 3 2 1 0 awb luminance lower limit 0 0 0 0 1 0 1 0 during cb/ cr frame mean value calculation, awb discards pixel of which luminance value is smaller than this register value. awb valid number of pixel [ awbvalid : 8c h : 02h ] 7 6 5 4 3 2 1 0 awb valid number of pixel 0 0 0 0 0 0 1 0 awb update when the number of valid color pixel is larger than (this valid value x 64).
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 54 - 2003 hynix semiconductor inc. dark bad pixel concealment mode [ dpcmode : 90 h : 01h ] 7 6 5 4 3 2 1 0 reserved dark bad pixel concealment mode 0 0 0 0 0 0 0 1 10 dark bad pixel concealment is always performed. 01 dark bad pixel concealment is performed when integration time (63h - 65h) exceeds dark bad integration time(91h - 93h) dark bad pixel concealment mode 11, 00 dark bad pixel concealment is turned off dark bad integration time high [ dpcinth : 91 h : 29h ] 7 6 5 4 3 2 1 0 dark integration time higher 0 0 1 0 1 0 0 1 dark bad integration time middle [ dpcintm : 92 h : dah ] 7 6 5 4 3 2 1 0 dark integration time middle 1 1 0 1 1 0 1 0 dark bad integration time low [ dpcintl : 93 h : 49h ] 7 6 5 4 3 2 1 0 dark integ ration time lower 1 1 0 0 1 0 0 1 dark bad integration time registers(91h - 93h) specify minimum integration time value(63h - 65h) where dark bad concealment operation is performed when dark bad pixel concealment mode is ? 01 (binary) ? .
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 55 - 2003 hynix semiconductor inc. dark g threshold [ d pcgth : 94 h : 20h ] 7 6 5 4 3 2 1 0 dark g threshold 0 0 1 0 0 0 0 0 the register value specify the current g pixel ? s differential value with neighboring g pixels, and is used to check whether current g pixel is dark bad pixel or not. dark r/b threshol d [ dpcgth : 95 h : 20h ] 7 6 5 4 3 2 1 0 dark r/b threshold 0 0 1 0 0 0 0 0 the register value specify the current r or b pixel ? s differential value with neighboring g pixels, and is used to check whether current r or b pixel is dark bad pixel or not. r eference of amp gain for dark bad pixel concealment [dpcgain : 96h : 38h] 7 6 5 4 3 2 1 0 reference of amp gain for dark bad pixel concealment 0 0 1 1 1 0 0 0 amp gain exceeds reference of amp gain for dark bad pixel concealment, dark bad concealment o peration is performed when dark bad pixel concealment mode is ? 01 contrast factor y [conty : 97h : 80h] 7 6 5 4 3 2 1 0 contrast factor y 1 0 0 0 0 0 0 0 contrast adjustment is performed for multiplying y data by contrast factor y, respectively. progr ammable range of contrast factor y is 0 ~ 2. cont y = y data * b<7:0>/128.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 56 - 2003 hynix semiconductor inc. pll control mode a [pctra : a0h : 01h] 7 6 5 4 3 2 1 0 reserved vco power down pll power down bypass mode 0 0 0 0 0 0 0 1 vco power down (active high) when vco power down is active, vco does not oscillate. for getting out of vco power down, vco initialization is required. pll power down (active high) when pll power down is active, digital circuits of pll do not operate and the charge pump circuits is disabled . also bypass mode or sleep mode(sctrb[4]) register is set to high, pll goes into sleep. 0 pll output clock is 1/f(ck). bypass mode 1 pll output clock is the same of pll input clock. * vco initialization to ensure the pr oper operation of the pll, the activation of vco initialization signal is required just after the deactivation of the vco power down. during power - up sequence vco initialization signal is recommended for more than 100ns. pll control mode b [pctrb : a1h : 1dh] 7 6 5 4 3 2 1 0 reserved post divisor charge pump bias 0 0 0 1 1 1 0 1 the value of post divisor according to the output frequency f(ck) post divisor min max 11 5mhz 12.5mhz 10 10mhz 25mhz 01 20mhz 50mhz 00 40mhz 100mhz
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 57 - 2003 hynix semiconductor inc. pll feedback divisor high [pfddivh : a4h : 00h] 7 6 5 4 3 2 1 0 pll feedback divisor high 0 0 0 0 0 0 0 0 pll feedback divisor low [pfddivl : a5h : 02h] 7 6 5 4 3 2 1 0 pll feedback divisor low 0 0 0 0 0 0 1 0 the operation frequency of pll is related to the proportion of reference(prefdiv) to feedback(pfddiv) divisor. f(ck) is actually determined by the following equation. ) ( ) ( ) ( ) ( divisor eference r divisor feedback ref f ck f * = f(ck) : freq uency of output f(ref) : frequency of pll input feedback divisor : pfddiv[13:0] + 2 reference divisor : 2 pixel number high [pxnumh : b9h : 04h] 7 6 5 4 3 2 1 0 pixel number high 0 0 0 0 0 1 0 0 pixel number low [pxnuml : bah : 00] 7 6 5 4 3 2 1 0 pixel number low 0 0 0 0 0 0 0 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 58 - 2003 hynix semiconductor inc. stable range variation [stthval : bbh : 30h] 7 6 5 4 3 2 1 0 stable range variation 0 0 1 1 0 0 0 0 frequency change variation [chthval : bch : 20h] 7 6 5 4 3 2 1 0 frequency change variation 0 0 1 0 0 0 0 0 afc mode control [afcmode : bdh : 00h] 7 6 5 4 3 2 1 0 reserved afc mode reserved afc enable 0 0 0 0 0 0 0 0 0 selected first afc algorithm afc mode 1 selected second afc algorithm 0 afc off afc enable 1 afc on 50hz integration t ime high [integ50h : c0h : 02h] 7 6 5 4 3 2 1 0 50hz integration time high 0 0 0 0 0 0 1 0 50hz integration time middle [integ50m : c1h : eeh] 7 6 5 4 3 2 1 0 50hz integration time middle
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 59 - 2003 hynix semiconductor inc. 1 1 1 0 1 1 1 0 50hz integration time low [integ50l : c2h : 00h] 7 6 5 4 3 2 1 0 50hz integration time low 0 0 0 0 0 0 0 0 60hz integration time high [integt60h : c3h : 02h] 7 6 5 4 3 2 1 0 60hz integration time high 0 0 0 0 0 0 1 0 60hz integration time middle [integt60m : c4h : 71h] 7 6 5 4 3 2 1 0 60hz integration time middle 0 0 0 0 0 0 0 0 60hz integration time low [integt60l :c5h : 00h] 7 6 5 4 3 2 1 0 60hz integration time low 0 0 0 0 0 0 0 0
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 60 - 2003 hynix semiconductor inc. anti - banding configuration for anti - banding mode to work correctly, the following registers sho uld be configured to the appropriate values. ae mode 60h anti - banding enable[7] ae anti - banding step 6a - 6ch (sensor clock frequency) / (2 x power line frequency) ae integration time limit 6d - 6fh the value should be multiples of ae anti - banding step wh en anti - banding is enabled, ae initializes integration time registers[63 - 65h] to 4 x anti - banding step value[6a - 6ch], and integration increment/decrement amount is set to anti - banding step value in order to remove anti - banding noise caused by intrinsic ene rgy waveform of light sources. banding noise is inherent in cmos image sensor that adopts rolling shutter scheme for image acquisition . frame timing for clear description of frame timing, clocks? acronym s are reminded in here again. < clock acronym defi nition > mcf : master clock frequency pcf : pll out clock frequency dcf : divided clock frequency scf : sensor clock frequency icf : image processing clock frequency lcf : line clock frequency vcf : video clock frequency < frame time calculation > c ore frame time is (idle slot + video height * lcp) and real frame time is resolved as follows. when integration time > core frame time, real frame time is ( integration time + vblank * lcp), otherwise is (core frame time + vblank * lcp).
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 61 - 2003 hynix semiconductor inc. 1. 5x5 color interp olation timing ( full size mode ) 5x5 color interpolation frame timing related parameters master clock frequency(mcf) 19.2 mhz pll out clock frequency(pcf) mcf*2 = 38.4mhz divided clock frequency(dcf) p cf/1 = 38.4 mhz sensor clock frequency(scf) dcf/ 2 = 19 .2 mhz sensor clock period(scp) 1/ 19.2 mhz = 52 ns window width 1152 window height 864 hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 136 6 scps output bus width 8bit vga video output frequency scf * 2 = 38.4 mhz final video ou tput size 1152x864 lcp(136 6 scps) isp dummy (6 scps) hsync (1152 scps) active data: 1152 ea idle slot(4lcps + (1024+hblank)*4) hblank (208 scps) vblank[vsync] (8 lcps) hold slot (integration time ? core frame time) real frame time core frame time video lines is active every lcp, that is, 864 video lines for 864 lcps if integration time < core frame time, real frame time is 4 * (208 + 1152+6 ) scps + 864 * ( 208 + 1152+6 ) scps + 8 * ( 208 + 1152+6 ) scps + 4 * (208+1024) = 1201544 scps = 0.0 62580s ec - > 15.979 frame per sec. e lse real frame time is integration time * scps + 8 * ( 208 + 1152 + 6 ) scps. hold slot in frame timing appears only if integration time is larger than core frame time .
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 62 - 2003 hynix semiconductor inc. 2. 5x5 color interpolation timing (1/4 sub - sampling mode) 5x5 color interpolation f rame timing related parameters master clock frequency(mcf) 19.2 mhz pll out clock frequency(pcf) mcf*2 = 38.4mhz divided clock frequency(dcf) p cf/1 = 38.4 mhz sensor clock frequency(scf) dcf/ 2 = 19.2 mhz sensor clock period(scp) 1/ 19.2 mhz = 52 ns window wi dth 576 window height 432 hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 136 6 scps output bus width 8bit vga video output frequency scf = 19.2 mhz final video output size 576 x 432 lcp(136 6 scps) isp dummy (6 scps) hsync (1152 scps) active data: 576 ea idle slot(4lcps + (1024+hblank)*4) hblank (208 scps) vblank[vsync] (8 lcps) hold slot (integration time ? core frame time) real frame time core frame time video lines is active every lcp, that is, 432 video lines for 432 lcps if integration t ime < core frame time, real frame time is 4 * (208 + 1152+6 ) scps + 432 * ( 208 + 1152+6 ) scps + 8 * ( 208 + 1152+6 ) scps + 4 * (208+1024) = 611432 scps = 0.0 31845s ec - > 31.402 frame per sec. else real frame time is integration time * scps + 8 * ( 208 + 1 152 + 6 ) scps. hold slot in frame timing appears only if integration time is larger than core frame time .
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 63 - 2003 hynix semiconductor inc. 3. 5x5 color interpolation timing ( 1/16 mode ) 5x5 color interpolation frame timing related parameters master clock frequency(mcf) 19.2 mhz pll out clock frequency(pcf) mcf*2 = 38.4mhz divided clock frequency(dcf) p cf/1 = 38.4 mhz sensor clock frequency(scf) dcf/ 2 = 19.2 mhz sensor clock period(scp) 1/ 19.2 mhz = 52 ns window width 288 window height 216 hblank value 208 vblank value 8 vsync mode line m ode line clock period(lcp) 136 6 scps output bus width 8bit vga video output frequency scf /2 = 9.6 mhz final video output size 288 x 216 lcp(136 6 scps) isp dummy (6 scps) hsync (1152 scps) active data: 288 ea idle slot(4lcps + (1024+hblank)*4) hblank (208 scps) vblank[vsync] (8 lcps) hold slot (integration time ? core frame time) real frame time core frame time video lines is active every lcp, that is, 216 video lines for 216 lcps if integration time < core frame time, real frame time is 4 * (208 + 1152+6 ) scps + 216 * ( 2 08 + 1152+6 ) scps + 8 * ( 208 + 1152+6 ) scps + 4 * (208+1024) = 316376 scps = 0.0 16478s ec - > 60.687frame per sec. else real frame time is integration time * scps + 8 * ( 208 + 1152 + 6 ) scps. hold slot in frame timing appears only if integration time is larger than core frame time .
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 64 - 2003 hynix semiconductor inc. 4. 5x5 color interpolation timing ( vgamode ) 5x5 color interpolation frame timing related parameters master clock frequency(mcf) 19.2 mhz pll out clock frequency(pcf) mcf*2 = 38.4mhz divided clock frequency(dcf) p cf/1 = 38.4 mhz sensor clock frequency(scf) dcf/ 2 = 19.2 mhz sensor clock period(scp) 1/ 19.2 mhz = 52 ns window width 640 window height 480 hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 136 6 scps output bus width 8bit vga video output f requency i rregular clock final video output size 640 x 480 lcp(136 6 scps) isp dummy (6 scps) hsync (1152 scps) active data: 640 ea idle slot(4lcps + (1024+hblank)*4) hblank (208 scps) vblank[vsync] (8 lcps) hold slot (integration time ? core frame time) real frame time core frame time video lines is active every lcp, that is, 480 video lines for 864 lcps if integration time < core frame time, real frame time is 4 * (208 + 1152+6 ) scps + 864 * ( 208 + 1152+6 ) scps + 8 * ( 208 + 1152+6 ) scps + 4 * (208+1024) = 1201544 scps = 0 .0 62580s ec - > 15.979 frame per sec. else real frame time is integration time * scps + 8 * ( 208 + 1152 + 6 ) scps. hold slot in frame timing appears only if integration time is larger than core frame time . vgamode frame rate is same as full size mode. a nd qvgamode has same frame rate.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 65 - 2003 hynix semiconductor inc. 5. 5x5 color interpolation timing (cifmode) 5x5 color interpolation frame timing related parameters master clock frequency(mcf) 19.2 mhz pll out clock frequency(pcf) mcf*2 = 38.4mhz divided clock frequency(dcf) p cf/1 = 3 8.4 mhz sensor clock frequency(scf) dcf/ 2 = 19.2 mhz sensor clock period(scp) 1/ 19.2 mhz = 52 ns window width 352 window height 288 hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 1 366 scps output bus width 8bit vga video outpu t frequency i rregular clock final video output size 352 x 288 lcp(1 366 scps) isp dummy (6 scps) hsync ( 1 152 scps) active data: 352 ea idle slot(4lcps + (1024+hblank)*4) hblank (208 scps) vblank[vsync] (8 lcps) hold slot (integration time ? core frame time) real frame time core frame time video lines is active every lcp, that is, 288 video lines for 864 lcps if integration time < core frame time, real frame time is 4 * (208 + 1152+6 ) scps + 864 * ( 208 + 1152+6 ) scps + 8 * ( 208 + 1152+6 ) scps + 4 * (208+1024) = 1201544 scps = 0.0 62580s ec - > 15.979 frame per sec. else real frame time is integration time * scps + 8 * ( 208 + 1152 + 6 ) scps. hold slot in frame timing appears only if integration time is larger than core frame time . qcifmode frame rate is same as cifmode frame rate.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 66 - 2003 hynix semiconductor inc. output data according to video mode output data according to video mode is controlled by configuring sensor control a[01h] and output format register[31h]. configurable options are specified again for your reference. sensor control a [sctra : 01h : 13h] 7 6 5 4 3 2 1 0 reserved x - flip y - flip video mode 0 0 0 1 0 0 1 1 output format [outfmt : 31h : 31h] 7 6 5 4 3 2 1 0 gamma - corrected bayer bayer 8bit output cb/b first y first ycbcr 4:4:4 / 4:2:2 rgb 4:4:4 rgb 565 8 bit output 0 0 1 1 0 0 0 1 output timings for general configurations are described below. slot named as ? x ? means that it is has no meaningful value and should be discarded. 8bit output is active, c[7:0] are always hi - z state. in case of cb or cr data, the digit stands for its sequence, respectively. for example, cb01 is equal to average of cb0 and cb1. 5x5 mode or sub - sampling(1/4, 1/16) mode 1. ycbcr 4:2:2 with 8bit output register bit configurations sensor control a : 5x5 mode or sub - sampling mode output format : 8bit output, y first, cb/b first
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 67 - 2003 hynix semiconductor inc. hsync mclk y6 cr45 y5 cb45 y4 cr23 y3 cb23 y2 cr01 y1 cb01 y0 x x y6 cr45 y5 cb45 y4 cr23 y3 cb23 y2 cr01 y1 cb01 y0 x x y6 cb46 y4 cr02 y2 cb02 y0 x y6 cb46 y4 cr02 y2 cb02 y0 x cr04 y4 cb04 y0 x cr04 y4 cb04 y0 x 1/4 sub - sampling video clock & output data 5x5 mode video clock & output data clk y[7:0] clk y[7:0] 1/16 sub - sampling video clock & output data clk y[7:0]
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 68 - 2003 hynix semiconductor inc. 2. ycbcr 4:2:2 with 16bit output register bit configurations sensor control a : 5x5 mode or sub - sampling mode output format : 16bit output, cb/b first hsync mclk y6 y4 y2 y0 x y6 y4 y2 y0 x 1/4 sub - sampling video clock & output data 5x5 mode video clock & output data cr46 cb46 cr02 cb02 x cr46 cb46 cr02 cb02 x y6 y5 y4 y3 y2 y1 y0 x y6 y5 y4 y3 y2 y1 y0 x cb67 cr45 cb45 cr23 cb23 cr01 cb01 x cb67 cr45 cb45 cr23 cb23 cr01 cb01 x y4 y0 x y4 y0 x cr04 cb04 x cr04 cb04 x clk y[7:0] c[7:0] clk y[7:0] c[7:0] 1/16 sub - sampling video clock & output data clk y[7:0] c[7:0]
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 69 - 2003 hynix semiconductor inc. 3. ycbcr 4:4:4 with 16bit output register bit configurations sensor control a : 5x5 mode or sub - sampling mode output format : 16bit output, y first, cb/b first hsync mclk y6 x y5 x y4 x y3 x y2 x y1 x y0 x x y6 x y5 x y4 x y3 x y2 x y1 x y0 x x y6 x y4 x y2 x y0 x y6 x y4 x y2 x y0 x x y4 x y0 x x y4 x y0 x 1/4 sub - sampling video clock & output data 5x5 mode video clock & output data clk clk 1/16 sub - sampling video clock & output data clk cb6 cr5 cb5 cr4 cb4 cr3 cb3 cr2 cb2 cr1 cb1 cr0 cb0 x x cb6 cr5 cb5 cr4 cb4 cr3 cb3 cr2 cb2 cr1 cb1 cr0 cb0 x x y[7:0] c[7:0] cb6 cr4 cb4 cr2 cb2 cr0 cb0 x cb6 cr4 cb4 cr2 cb2 cr0 cb0 x y[7:0] c[7:0] cr4 cb4 cr0 cb0 x cr4 cb4 cr0 cb0 x y[7:0] c[7:0]
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 70 - 2003 hynix semiconductor inc. 4. rgb 565 with 8bit output register bit configurations sensor control a : 5x5 mode or sub - sampling mode output format : 8bit output, cb/b first, rgb565 hsync mclk rg6 gb5 rg5 gb4 rg4 gb3 rg3 gb2 rg2 bg1 rg1 gb0 rg0 x x rg6 gb5 rg5 gb4 rg4 gb3 rg3 gb2 rg2 bg1 rg1 gb0 rg0 x x rg6 gb4 rg4 gb2 rg2 gb0 rg0 x rg6 gb4 rg4 gb2 rg2 gb0 rg0 x gb4 rg4 gb0 rg0 x gb4 rg4 gb0 rg0 x 1/4 sub - sampling video clock & output data 5 x5 mode video clock & output data clk clk 1/16 sub - sampling video clock & output data clk y[7:0] y[7:0] y[7:0] { g0[4:2]b0[7:3]} { r0[7:3]g0[7:5]} { g0[4:2]b0[7:3]} { r0[7:3]g0[7:5]}
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 71 - 2003 hynix semiconductor inc. 5. rgb 565 with 16bit output register bit configurations sensor control a : 5x5 mode or sub - sampling mode output format : 16bit output, cb/b first, rgb565 hsync mclk 5 x5 mode video clock & output data { r0[7:3]g0[7:5]} { r0[7:3]g0[7:5]} rg6 rg5 rg4 rg3 rg2 rg1 rg0 x rg6 rg5 rg4 rg3 rg2 rg1 rg0 x clk gb6 gb5 gb4 gb3 gb2 gb1 gb0 x gb6 gb5 gb4 gb3 gb2 gb1 gb0 x y[7:0] c[7:0] { g0[4:2]b0[7:3]} { g0[4:2]b0[7:3]} rg6 rg4 rg2 rg0 x rg6 rg4 rg2 rg0 x 1/4 sub - sampling video clock & output data gb6 gb4 gb2 gb0 x gb6 gb4 gb2 gb0 x rg4 rg0 x rg4 rg0 x gb4 gb0 x gb4 gb0 x clk y[7:0] c[7:0] 1/16 sub - sampling video clock & output data clk y[7:0] c[7:0]
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 72 - 2003 hynix semiconductor inc. 6. rgb 4:4:4 with 16bit output register bit configurations sensor control a : 5x5 mode or sub - sampling mode outp ut format : 16bit output, cb/b first, rgb4:4:4 hsync mclk g6 x g5 x g4 x g3 x g2 x g1 x g0 x x g6 x g5 x g4 x g3 x g2 x g1 x g0 x x g6 x g4 x g2 x g0 x g6 x g4 x g2 x g0 x x g4 x g0 x x g4 x g0 x 1/4 sub - sampling video clock & output data 5x5 mode video clock & output data clk clk 1/16 sub - sampling video clock & output data clk b6 r5 b5 r4 b4 r3 b3 r2 b2 r1 b1 r0 b0 x x b6 r5 b5 r4 b4 r3 b3 r2 b2 r1 b1 r0 b0 x x y[7:0] c[7:0] b6 r4 b4 r2 b2 r0 b0 x b6 r4 b4 r2 b2 r0 b0 x y[7:0] c[7:0] r4 b4 r0 b0 x r4 b4 r0 b0 x y[7:0] c[7:0]
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 73 - 2003 hynix semiconductor inc. vga mode or qvga mode 1. ycbcr 4:2:2 with 8bit output register bit configurations sensor control a : vga mode or qvga mode output format : 8bit output, y first, cb/b first 2. ycbcr 4:2:2 with 16bit output register bit configurations sensor control a : vga mode or qvga mode output format : 16bit output, cb/b first hsync mclk vga mode video clock & output data clk y[7:0] qvga mode video clock & output data cr 89 y9 cb89 y7 cr67 y8 cb67 y10 y6 cr45 y5 cb 45 y4 cr23 y3 cb23 y2 cr01 y1 cb01 y0 x cr 89 y9 cb89 y7 cr67 y8 cb67 y10 y6 cr45 y5 cb 45 y4 cr23 y3 cb23 y2 cr01 y1 cb01 y0 x cr 89 y9 cb89 x x y8 x x x cr45 y5 cb 45 y4 x x x x cr01 y1 cb01 y0 x cr 89 y9 cb89 x x y8 x x x cr45 y5 cb 45 y4 x x x x cr01 y1 cb01 y0 x clk y[7:0] hsync mclk vga mode video clock & output data clk y[7:0] c[7:0] qvga mode video clock & output data clk rg9 rg7 rg8 rg10 rg6 rg5 rg4 rg3 rg2 rg1 rg0 x rg9 rg7 rg8 rg10 rg6 rg5 rg4 rg3 rg2 rg1 rg0 x gb9 gb7 gb8 gb10 gb6 gb5 gb4 gb3 gb2 gb1 gb0 x gb9 gb7 gb8 gb10 gb6 gb5 gb4 gb3 gb2 gb1 gb0 x y[7:0] c[7:0] y9 x y8 y10 x y5 y4 x x y1 y0 x y9 x y8 y10 x y5 y4 x x y1 y0 x cr89 x cb89 x cr45 cb45 x x cr01 cb01 x cr89 x cb89 x cr45 cb45 x x cr01 cb01 x
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 74 - 2003 hynix semiconductor inc. 3. ycbcr 4:4:4 with 16bit output register bit configurations sensor control a : vga mode or qvga mode output format : 16bit output, y first, cb/b first 4. rgb 565 with 8bit output register bit configurations sensor control a : vga mode or qvga mode output format : 8bit output, cb/b first, rgb565 hsync mclk vga mode video clock & output data clk y[7:0] c[7:0] qvga mode video clock & output data clk x y9 x y7 x y8 x y10 y6 x y5 x y4 x y3 x y2 x y1 x y0 x x y9 x y7 x y8 x y10 y6 x y5 x y4 x y3 x y2 x y1 x y0 x cr9 cb9 cr8 cb7 cr7 cb8 cr6 cb10 cb6 cr5 cb5 cr4 c b4 cr3 cb3 cr2 cb2 cr1 cb1 cr0 cb0 x cr9 cb9 cr8 cb7 cr7 cb8 cr6 cb10 cb6 cr5 cb5 cr4 c b4 cr3 cb3 cr2 cb2 cr1 cb1 cr0 cb0 x y[7:0] c[7:0] x x x x x y8 x y10 y6 x x x y4 x x x y2 x x x y0 x x x x x x y8 x y10 y6 x x x y4 x x x y2 x x x y0 x x x cr8 x x cb8 cr6 cb10 cb6 x x cr4 c b4 x x cr2 cb2 x x cr0 cb0 x x x cr8 x x cb8 cr6 cb10 cb6 x x cr4 c b4 x x cr2 cb2 x x cr0 cb0 x hsync mclk vga mode video clock & output data clk y[7:0] qvga mode video clock & output data clk gb 9 rg 9 gb8 rg7 gb7 rg8 gb6 rg10 rg6 gb5 rg5 gb 4 rg 4 gb3 rg3 gb2 rg2 gb1 rg1 gb0 rg0 x gb 9 rg 9 gb8 rg7 gb7 rg8 gb6 rg10 rg6 gb5 rg5 gb 4 rg 4 gb3 rg3 gb2 rg2 gb1 rg1 gb0 rg0 x y[7:0] x x gb8 x x rg8 gb6 rg10 rg6 x x gb 4 rg 4 x x gb2 rg2 x x gb0 rg0 x x x gb8 x x rg8 gb6 rg10 rg6 x x gb 4 rg 4 x x gb2 rg2 x x gb0 rg0 x
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 75 - 2003 hynix semiconductor inc. 5. rgb 565 with 16bit output register bit configurations sensor control a : vga mode or qvga mode outp ut format : 16bit output, cb/b first, rgb565 6. rgb 4:4:4 with 16bit output register bit configurations sensor control a : vga mode or qvga mode output format : 16bit output, cb/b first, rgb4:4:4 hsync mclk vga mode video clock & output data clk y[7:0] c[7:0] qvga mode video clock & output data clk rg9 rg7 rg8 rg10 rg6 rg5 rg4 rg3 rg2 rg1 rg0 x rg9 rg7 rg8 rg10 rg6 rg5 rg4 rg3 rg2 rg1 rg0 x gb9 gb7 gb8 gb10 gb6 gb5 gb4 gb3 gb2 gb1 gb0 x gb9 gb7 gb8 gb10 gb6 gb5 gb4 gb3 gb2 gb1 gb0 x y[7:0] c[7:0] rg9 x rg8 x x rg5 rg4 x x rg1 rg0 x rg9 x rg8 x x rg5 rg4 x x rg1 rg0 x gb9 x gb8 x x gb5 gb4 x x gb1 gb0 x gb9 x gb8 x x gb5 gb4 x x gb1 gb0 x hsync mclk vga mode video clock & output data clk y[7:0] c[7:0] qvga mode video clock & output data clk x g9 x g7 x g8 x g10 g6 x g5 x g4 x g3 x g2 x g1 x g0 x x g9 x g7 x g8 x g10 g6 x g5 x g4 x g3 x g2 x g1 x g0 x r9 b9 r8 b7 r7 b8 r6 b10 b6 r5 b5 r4 b4 r3 b3 r2 b2 r1 b1 r0 b0 x r9 b9 r8 b7 r7 b8 r6 b10 b6 r5 b5 r4 b4 r3 b3 r2 b2 r1 b1 r0 b0 x y[7:0] c[7:0] x x x x x g8 x g10 g6 x x x g4 x x x g2 x x x g0 x x x x x x g8 x g10 g6 x x x g4 x x x g2 x x x g0 x x x r8 x x b8 r6 b10 b6 x x r4 b4 x x r2 b2 x x r0 b0 x x x r8 x x b8 r6 b10 b6 x x r4 b4 x x r2 b2 x x r0 b0 x
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 76 - 2003 hynix semiconductor inc. cif mode or qcif mode 1. ycbcr 4:2:2 with 8bit output regis ter bit configurations sensor control a : cif mode or qcif mode output format : 8bit output, y first, cb/b first 2. ycbcr 4:2:2 with 16bit output register bit configurations sensor control a : cif mode or qcif mode output format : 16bit output, cb/b first hsync cb45 y4 cr23 y3 cb23 y2 cr01 y1 cb01 y0 x cb45 y4 cr23 y3 cb23 y2 cr01 y1 cb01 y0 x mclk cb01 y4 x x x x cr01 y1 cb01 y0 x cb01 y4 x x x x cr01 y1 cb01 y0 x cif mode video clock & output data qcif mode video clock & output data clk y[7:0] clk y[7:0] hsync y4 y3 y2 y1 y0 x y4 y3 y2 y1 y0 x mclk y4 x x y1 y0 x y4 x x y1 y0 x cif mode video clock & output data qcif mode video clock & output data clk y[7:0] c[7:0] clk y[7:0] c[7:0] cb45 cr23 cb23 cr01 cb01 x cb45 cr23 cb23 cr01 cb01 x cb45 x x cr01 cb01 x cb45 x x cr01 cb01 x
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 77 - 2003 hynix semiconductor inc. 3. ycbcr 4:4:4 with 16bit output register bit configurations sensor control a : cif mode or qcif mode output format : 16bit output, y first, cb/b first 4. rgb 565 with 8bit output register bit configurations sensor control a : cif mode or qcif mode output format : 8bit output, cb/b first, rgb565 hsync mclk x y4 x y3 x y2 x y1 x y0 x x y4 x y3 x y2 x y1 x y0 x x y4 x x x x x y1 x y0 x x y4 x x x x x y1 x y0 x cif mode video clock & output data qcif mode video clock & output data clk y[7:0] c[7:0] clk y[7:0] c[7:0] cr4 cb4 cr3 cb3 cr2 cb2 cr1 cb1 cr0 cb0 x cr4 cb4 cr3 cb3 cr2 cb2 cr1 cb1 cr0 cb0 x cr4 cb4 x x x x cb1 cb1 cr0 cb0 x cr4 cb4 x x x x cb1 cb1 cr0 cb0 x hsync mclk gb4 rg4 gb3 rg3 gb2 rg2 gb1 rg1 gb0 rg0 x gb4 rg4 gb3 rg3 gb2 rg2 gb1 rg1 gb0 rg0 x gb4 rg4 x x x x gb1 rg1 gb0 rg0 x gb4 rg4 x x x x gb1 rg1 gb0 rg0 x cif mode video clock & output data qcif mode video clock & output data clk y[7:0] clk y[7:0]
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 78 - 2003 hynix semiconductor inc. 5. rgb 565 with 16bit output register bit configurations sensor control a : cif mode or qcif mode output format : 16bit output, cb/b first, rgb565 6. rgb 4:4:4 with 16bit output register bit configurations sensor c ontrol a : cif mode or qcif mode output format : 16bit output, cb/b first, rgb4:4:4 rg4 rg3 rg2 rg1 rg0 x rg4 rg3 rg2 rg1 rg0 x rg4 x x rg1 rg0 x rg4 x x rg1 rg0 x cif mode video clock & output data qcif mode video clock & output data clk y[7:0] c[7:0] clk y[7:0] c[7:0] gb4 gb3 gb2 gb1 gb0 x gb4 gb3 gb2 gb1 gb0 x gb4 x x gb1 gb0 x gb4 x x gb1 gb0 x hsync mclk hsync mclk x g4 x g3 x g2 x g1 x g0 x x g4 x g3 x g2 x g1 x g0 x x g4 x x x x x g1 x g0 x x g4 x x x x x g1 x g0 x cif mode video clock & output data qcif mode video clock & output data clk y[7:0] c[7:0] clk y[7:0] c[7:0] r4 b4 r3 b3 r2 b2 r1 b1 r0 b0 x r4 b4 r3 b3 r2 b2 r1 b1 r0 b0 x r4 b4 x x x x r1 b1 r0 b0 x r4 b4 x x x x r1 b1 r0 b0 x
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 79 - 2003 hynix semiconductor inc. bayer data format sctra[2:0] is set to bayer mode - when bayer output mode is selected, window width x window height raw image data are produced with the following sequ ence. after vsync goes low state, the first hsync line of a frame is activated with b pixel data appearing first when both of column start address and row start address are even. y[7:0] even line vclk y[7:0] odd line hsync x b g b g b g x g r g r g r
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 80 - 2003 hynix semiconductor inc. i2c chip interface the serial bus interface co nsists of the sda (serial data) and sck (serial clock) pins. HV7151SP sensor can operate only as a slave. the sck only c ontrols the serial interface . however, mclk should be supplied and reset should be high signal during controlling the serial interface . th e start condition is that logic transition (high to low) on the sda pin while the sck pin is at high state. the stop condition is that logic transition (low to high) on the sda pin while the sck pin is at high state. to generate acknowledge signal, the sen sor drives the sda low when the sck pin is at high state. every byte consists of 8 bits. each byte transferred on the bus must be followed by an acknowledge. the most significant bit of the byte should always be transmitted first. register write se quences one byte write s 22h a 01h a 04h a p *1 *2 *3 *4 *5 *6 *7 *8 set " sensor control a " register into window mode *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit] *3. read: acknowledge from sensor *4. drive: 01 h [sub - address] *5. read: acknowledge from sensor *6. drive: 04h [video mode : vga] *7. read: acknowledge from sensor *8. drive: i2c stop condition 1 2 8 9 ack msb lsb sda sck start 1 2 8 9 ack stop
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 81 - 2003 hynix semiconductor inc. multiple byte write using auto address increment s 22h a 0c h a 03 h a 60 h a p *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 set " ae integration step high/low " register as 5161 h with auto address increment *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit] *3. read: acknowledge from sensor *4. drive: 0c h [sub - address] *5. read: acknowledg e from sensor *6. drive: 03 h [ window height upper ] *7. read: acknowledge from sensor *8. drive: 60 h [ window height lower ] *9. read: acknowledge from sensor *10. drive : i2c stop condition register read sequence s 22h a 1c h a s 23h a data of 07h a p *1 * 2 *3 *4 *5 *6 *7 *8 *9 *10 *11 read "reset level clamp " register from HV7151SP *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit(be careful. r/w=0)] *3. read: acknowledge from sensor *4. drive: 1 c h [sub - address] *5. rea d: acknowledge from sensor *6. drive: i 2 c start condition *7. drive: 23h(001_0001 + 1) [device address + r/w bit(be careful. r/w=1)] *8. read: acknowledge from sensor *9. read: read ? reset level clamp ? from sensor *10. drive: acknowledge to sensor . i f the re is more data bytes to read, sda should be driven to low and data read states(*9, *10) is repeated. otherwise sda should be driven to high to prepare for the read transaction end. *11. drive : i2c stop condition
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 82 - 2003 hynix semiconductor inc. ac/dc characteristics absolute maximum ra tings symbol parameter units min. max. viopp i/o block supply voltage volts - 0.3 3.3 vdpp internal digital s upply voltage volts - 0.3 2.5 vapp analog supply voltage volts - 0.3 2.5 vipp input signal voltage volts - 0.3 3.3 top operating temperature c - 10 50 tst storage temperature c - 30 80 caution: stresses exceeding the absolute maximum ratings may induce failure. dc operating conditions symbol parameter units min. max. load[pf] notes vio i/o block supply voltage volt 2.3 2.8 v dd internal op eration supply voltage volt 1.6 2.0 v ih input voltage logic "1" volt 2. 3 2.5 6.5 v il input voltage logic "0" volt 0 0.8 6.5 v oh output voltage logic "1" volt 2. 15 vio 60 v ol output voltage logic "0" volt 0.4 60 i o h output high current ma - 4 6 0 i ol output low current ma 4 60 t a ambient operating temperature celsius - 10 50
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 83 - 2003 hynix semiconductor inc. ac operating conditions symbol parameter max operation frequency units notes mclk main clock frequency 1) pll off : 38.4 2) pll on : ) ( ) (re 4 . 38 divisor feedback divisor ference * mhz 1 ,2,3 sck i 2 c clock frequency 4 00 k hz 4 1. mclk may be divided by internal clock division logic for easy integration with high speed video codec system. 2. reference divider and feedback divider is registers a3h and a4h, a5h, respectively . 3. frame rate : 15 fr ames/sec at 38.4mhz and pll off , hblank = 208, vblank = 8 4. sck is driven by host processor. for the detail serial bus timing, refer to i2c chip interface section o utput ac c haracteristics all output timing delays are measured with output load 60[pf]. out put delay include s the internal clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. due to the variable valid time delay of the output, video output signals y[7:0], c[7:0], hs ync, and vsync may be latched in the negative edge of v clk for the stable data transfer between the image sensor and video codec . y/c[7:0] vclk x data 0 data 1 data 2 hsync data 3 3ns
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 84 - 2003 hynix semiconductor inc. i2c bus timing sda sck stop start tbuf tlow tr thd;sta thd;dat thigh tsu;dat tsu;sta tsu;sto stop start tf thd;sta parameter symbol min. max. unit sck clock frequ ency f sck 0 4 00 khz time that i 2 c bus must be free before a new transmission can start t buf 1.2 - us hold time for a start t hd ;s ta 1.0 - us low period of sck t low 1.2 - us high period of sck t high 1.0 - us setup time for start t su ;s ta 1.2 - us data hold time t hd ;d at 0.1 - us data setup time t su ;d at 250 - ns rise time of both sda and sck t r - 250 ns fall time of both sda and sck t f - 300 ns setup time for stop t su ;s to 1.2 - us capacitive load of sck/sda c b - - pf
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 85 - 2003 hynix semiconductor inc. electro - o ptical c haracteristics parameter units min. typical max. target sensitivity mv / lux ? sec 1175 2200 dark signal mv / sec tbd under 1 dark shading mv/sec tbd output signal shading % tbd output saturation signal mv 610 600 power consumption (normal mode) mw 60
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 86 - 2003 hynix semiconductor inc. package information
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 87 - 2003 hynix semiconductor inc.
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 88 - 2003 hynix semiconductor inc. reference circuit information
HV7151SP cmos image sensor confidential with image signal processing this document is a gene ral product description and is subject to change without notice. hynix semiconductor inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 89 - 2003 hynix semiconductor inc. memo h ynix semiconductor in c. system ic sbu * contact point * mt marketing team 15floor, hynix youngdong bldg. 891 daechi - dong kangnam - gu seoul 135 - 7 38 republic of korea tel: 82 - 2 - 3459 - 5579 fax: 82 - 2 - 3459 - 5580 e - mail : suyeon.moon@hynix.com

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